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2012 (Vol. 4, Issue: 01)
Article Information:

Delay Reduction in Optimized Reversible Multiplier Circuit

Mohammad Assarian, Majid Haghparast and Keivan Navi
Corresponding Author:  Majid Haghparast 

Key words:  Circuit delay, critical path, nanotechnology, reversible logic circuit, reversible logic gate, reversible multiplier,
Vol. 4 , (01): 27-32
Submitted Accepted Published
2011 August, 26 2011 September, 30 2012 January, 01
Abstract:

In this study a novel reversible multiplier is presented. Reversible logic can play a significant role in computer domain. This logic can be applied in quantum computing, optical computing processing, DNA computing, and nanotechnology. One condition for reversibility of a computable model is that the number of input equate with the output. Reversible multiplier circuits are the circuits used frequently in computer system. For this reason, optimization in one reversible multiplier circuit can reduce its volume of hardware on one hand and increases the speed in a reversible system on the other hand. One of the important parameters that optimize a reversible circuit is reduction of delays in performance of the circuit. This paper investigates the performance characteristics of the gates, the circuits and methods of optimizing the performance of reversible multiplier circuits. Results showed that reduction of the reversible circuit layers has lead to improved performance due to the reduction of the propagation delay between input and output period. All the designs are in the nanometric scales.
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  Cite this Reference:
Mohammad Assarian, Majid Haghparast and Keivan Navi, 2012. Delay Reduction in Optimized Reversible Multiplier Circuit.  Research Journal of Applied Sciences, Engineering and Technology, 4(01): 27-32.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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