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2012 (Vol. 4, Issue: 07)
Article Information:

Single Core Hardware Modeling of Built-in-Self-Test for System on Chip Design

M.D. Mamun, M.S. Amin and J. Jalil
Corresponding Author:  Md. Syedul Amin 

Key words:  Built-in-self-test, circuit under test, design for testability, latches, system on chip, VHDL,
Vol. 4 , (07): 819-824
Submitted Accepted Published
2011 November, 15 2011 December, 09 2012 April, 01

This study describes a hardware modeling environment of built-in-self-test (BIST) for System on Chip (SOC) testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL) model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. The design is modularized and each module is modeled individually using hardware description language VHDL. This is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit, which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications with a maximum clock frequency of 31.4 MHz.
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  Cite this Reference:
M.D. Mamun, M.S. Amin and J. Jalil, 2012. Single Core Hardware Modeling of Built-in-Self-Test for System on Chip Design.  Research Journal of Applied Sciences, Engineering and Technology, 4(07): 819-824.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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