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2013 (Vol. 5, Issue: 02)
Article Information:

Object Oriented Model for Evaluation of On-Chip Networks

Sheraz Anjum, Ehsan Ullah Munir, Waqas Anwar and Nadeem Javaid
Corresponding Author:  Sheraz Anjum 

Key words:  2D-diagonal-mesh, network simulator-2, networks on chip, object oriented model, traffic models, ,
Vol. 5 , (02): 353-356
Submitted Accepted Published
April 08, 2012 April 30, 2012 January 11, 2013
Abstract:

The Network on Chip (NoC) paradigm is rapidly replacing bus based System on Chip (SoC) designs due to their inherent disadvantages such as non-scalability, saturation and congestion. Currently very few tools are available for the simulation and evaluation of on-chip architectures. This study proposes a generic object oriented model for performance evaluation of on-chip interconnect architectures and algorithms. The generic nature of the proposed model can help the researchers in evaluation of any kind of on-chip switching networks. The model was applied on 2D-Mesh and 2D-Diagonal-Mesh on-chip switching networks for verification and selection of best out of both the analyzed architectures. The results show the superiority of 2D-Diagonal-Mesh over 2D-Mesh in terms of average packet delay.
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  Cite this Reference:
Sheraz Anjum, Ehsan Ullah Munir, Waqas Anwar and Nadeem Javaid, 2013. Object Oriented Model for Evaluation of On-Chip Networks.  Research Journal of Applied Sciences, Engineering and Technology, 5(02): 353-356.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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