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2013 (Vol. 5, Issue: 05)
Article Information:

Arithmetic CMOS Design with Better Properties

E. Poovannan, P. Ramani and M. Ramkumar Prabhu
Corresponding Author:  E. Poovannan 

Key words:  Arithmetic circuit, full adder, multiplier, low power, very Large-scale integration (VLSI), ,
Vol. 5 , (05): 1491-1495
Submitted Accepted Published
March 14, 2012 April 08, 2012 February 11, 2013

This study concentrate on the considerable improvement in speed , propagation delay and power consumption by using 14T CMOS. Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In addition to its main task, which is adding two numbers, it participates in many other useful operations such as subtraction, multiplication, division,, address calculation,..etc. In most of these systems the adder lies in the critical path that determines the overall speed of the system. So enhancing the performance of the 1-bit full adder cell (the building block of the adder) is a significant goal. Demands for the low power VLSI have been pushing the development of aggressive design methodologies to reduce the power consumption drastically. To meet the growing demand, we propose a new low power adder cell by sacrificing the MOS Transistor count that reduces the serious threshold loss problem, considerably increases the speed and decreases the power when compared to the static energy recovery full (SERF) adder. So a new improved 14T CMOS l-bit full adder cell is presented in this paper. Results show 50% improvement in threshold loss problem, 45% improvement in speed and considerable power consumption over the SERF adder and other different types of adders with comparable performance.
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  Cite this Reference:
E. Poovannan, P. Ramani and M. Ramkumar Prabhu, 2013. Arithmetic CMOS Design with Better Properties.  Research Journal of Applied Sciences, Engineering and Technology, 5(05): 1491-1495.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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