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2013 (Vol. 5, Issue: 08)
Article Information:

Design of a High Speed Low Power 2s Complement Adder Circuit

Habsah Abdul Shaer, Md. Mamun, Mohd. Marufuzzaman and H. Husain
Corresponding Author:  Habsah Abdul Shaer 

Key words:  CMOS, full adder, 2s complement adder, PTL, PDP, XOR,
Vol. 5 , (08): 2556-2564
Submitted Accepted Published
August 07, 2012 September 03, 2012 March 15, 2013

Most modern computers use the 2s complement system to represent negative numbers and to perform subtraction by using adder circuit. Several criteria such as speed, power consumption and propagation delay must be taken into account in the design of arithmetic circuits. This study proposed a technique to build an improved 2s complement adder circuit using the combination of existing XOR and new full adder structure. The design is implemented in CEDEC 0.18 m CMOS process at 3.3v supply voltage. The results showed that the circuit is required only 0.83nW with maximum delay of 50.08 ns for 1-bit adder. Delay and power dissipation of different adder circuits for various numbers of inputs are also simulated and analyzed. Comparison study showed that the design is given a better critical delay and low power dissipation compared to other research studies. Moreover, because of using less number of transistors, the design occupied small die area. The compact size of the circuit with low power and low propagation delay is highly required in arithmetic circuits.
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  Cite this Reference:
Habsah Abdul Shaer, Md. Mamun, Mohd. Marufuzzaman and H. Husain, 2013. Design of a High Speed Low Power 2s Complement Adder Circuit.  Research Journal of Applied Sciences, Engineering and Technology, 5(08): 2556-2564.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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