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Abstract
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Article Information:
Design of an 8-cell Dual Port SRAM in 0.18-μm CMOS Technology
Mohammad Mahdi Ariannejad, Mamun Bin IbneReaz, Md. Syedul Amin and F.H. Hashim
Corresponding Author: Mamun Bin IbneReaz
Submitted: August 07, 2012
Accepted: September 03, 2012
Published: March 15, 2013 |
Abstract:
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Low power and low area Static Random Access Memory (SRAM) is essential for System on Chip (SoC) technology. Dual-Port (DP) SRAM greatly reduces the power consumption by full current-mode techniques for read/write operation and the area by using Single-Port (SP) cell. An 8 bit DP-SRAM is proposed in this study. Negative bit-line technique during write has been utilized for write-assist solutions. Negative voltage is generated on-chip using capacitive coupling. The proposed circuit design topology does not affect the read operation for bit interleaved architectures enabling high-speed operation. Designed in 0.18-μm CMOS process, the area is only 1.2 times of the SP-SRAM and its power is 1.3 times of the SP-SRAM when the two ports simultaneously work at the same frequency. Simulation results and comparative study of the present scheme with state of-the art conventional schemes proposed in the literature for 45 nm CMOS technology show that the proposed scheme is superior in terms of process-variations impact, area overhead, timings and dynamic power consumption. The proposed negative bit-line technique can be used to improve the write ability of 6 T Single-Port (SP) as well as 8 T DP and other multiport SRAM cells.
Key words: Demultiplexer, memory cell, negative bit-line, SRAM, tri-state buffer, ,
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Cite this Reference:
Mohammad Mahdi Ariannejad, Mamun Bin IbneReaz, Md. Syedul Amin and F.H. Hashim, . Design of an 8-cell Dual Port SRAM in 0.18-μm CMOS Technology. Research Journal of Applied Sciences, Engineering and Technology, (08): 2565-2568.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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