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2013 (Vol. 5, Issue: 10)
Article Information:

Designs and Implementations of Low-Leakage Digital Standard Cells Based on Gate-Length Biasing

Jindan Chen and Jianping Hu
Corresponding Author:  Jianping Hu 

Key words:  Digital standard cells, gate-length biasing techniques integrated circuits, low-leakage designs, , , ,
Vol. 5 , (10): 2957-2963
Submitted Accepted Published
September 15, 2012 October 31, 2012 March 25, 2013
Abstract:

In this study, a minimum set of low-power digital standard cells for low-leakage applications are developed and introduced into SMIC (Semiconductor Manufacturing International Corporation) 130 nm CMOS libraries, which include basic logic gates such as inverter, NAND, NOR, XOR, XNOR and flip-flop. The inverter, NAND, NOR and flip-flop standard cells based on the gate-length biasing technique are proposed to achieve low Energy Delay Product (EDP). The XOR and XNOR standard cells are optimized based on transistor-level. All circuits are simulated with HSPICE at a SMIC 130nm CMOS technology by a 1.2V supply voltage. The proposed several standard cells attain large leakage reductions. A mode-10 counter is verified with the proposed standard cells by using commercial EDA tools. The leakage and total dynamic power dissipations of the mode-10 counter using the proposed standard cells provide a reduction of 21.27 and 3.06%, respectively. The results indicate the proposed standard cells are a good choose in low leakage applications.
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  Cite this Reference:
Jindan Chen and Jianping Hu, 2013. Designs and Implementations of Low-Leakage Digital Standard Cells Based on Gate-Length Biasing.  Research Journal of Applied Sciences, Engineering and Technology, 5(10): 2957-2963.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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