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2013 (Vol. 5, Issue: 21)
Article Information:

Designs of 2P-2P2N Energy Recovery Logic Circuits

Jianping Hu and Binbin Liu
Corresponding Author:  Jianping Hu 

Key words:  2P-2P2N, adiabatic circuits, leakage power, low power, near-threshold techniques, ,
Vol. 5 , (21): 4977-4982
Submitted Accepted Published
July 31, 2012 September 17, 2012 May 20, 2013

In this study, we propose a P-type energy recovery logic named as 2P-2P2N to reduce the leakage dissipations in nanometer CMOS processes with gate oxide materials. A combinational circuit 4-bit carry look-ahead adder and a sequential circuit D flip-flop are realized. Near threshold techniques are used to reduce their power dissipations. All the circuits are simulated by HSPICE using 65 nm PTM technology. The results show that the 2P-2P2N circuits adopting near threshold techniques consume about 82.9-88.4% less power than conventional static CMOS logic and about 45.6-53.2% less power than 2N-2N2P adiabatic logic.
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  Cite this Reference:
Jianping Hu and Binbin Liu, 2013. Designs of 2P-2P2N Energy Recovery Logic Circuits.  Research Journal of Applied Sciences, Engineering and Technology, 5(21): 4977-4982.
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ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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