|
Abstract
|
Article Information:
Performance Analysis on Router Arbitration for On-chip Networking
G. Selvaraj and K.R. Kashwan
Corresponding Author: G. Selvaraj
Submitted: December 28, 2013
Accepted: January 20, 2014
Published: August 15, 2014 |
Abstract:
|
This study is a comprehensive report on performance analyses of Round Robin and matrix arbitrations to enhance the reliability of on-chip networks. Arbiter is used in Network-on-Chip (NoC) router when number of input ports requested is the same as output ports. If many inputs are requested for same output port, the matrix arbiter deals it by forming a 5×5 matrix based on input and output ports. Next, it allots the priority to the requested input ports and simultaneously generates a control signal for selecting the input port to send the packet to output port. The Robin arbiter generates the grant signal on the basis of priority allotted to the input ports. The simulation results of arbitration analysis shows that the router design of front end model consumes less power by 8% and occupies smaller area by 3% on chip. The area on chip is around 64% of available area using Round Robin arbitration compare to that of matrix arbitration. This study also implements hamming distance in order to check the error free data transmission of the NoC router.
Key words: Arbiter, hamming code, matrix arbiter, network-on-chip, round robin arbiter, router,
|
|
Abstract
|
PDF
|
HTML |
|
Cite this Reference:
G. Selvaraj and K.R. Kashwan, . Performance Analysis on Router Arbitration for On-chip Networking. Research Journal of Applied Sciences, Engineering and Technology, (6): 706-713.
|
|
|
|
 |
ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
 |
| Information |
|
|
|
|
| Sales & Services |
|
|
|
|
