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Abstract
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Article Information:
PRINCE IP-core on Field Programmable Gate Arrays (FPGA)
Yasir Amer Abbas, Razali Jidin, Norziana Jamil, Muhammad Reza Z’aba and Mohd Ezanee Rusli
Corresponding Author: Yasir Amer Abbas
Submitted: January 31, 2015
Accepted: March 7, 2015
Published: July 20, 2015 |
Abstract:
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This study presents a high execution-speed and low-resource hardware IP-Core of PRINCE light weight block cipher on a Field Programmable Gate Arrays (FPGA). The new FPGA IP-core is to speed-up the performance of PRINCE, superseding software implementation that is typically slow and inefficient. The design of this IP core is based on concurrent concept in encrypting blocks of 64 bits data, in that each block is executed within one clock cycle, resulting in high throughput and low latency. Though this IP core encrypts data at high speed processing, it consumes relatively low power. The hardware design can allow encryption, decryption and key schedule to utilize identical hardware components, in order to reduce further the FPGA resources. This efficient PRINCE hardware architecture has been coded using Very High speed integrated circuit Hardware Description Language (VHDL). Also, a bus interface has been included as part of PRINCE IP core to allow it to communicate with an on-chip microprocessor. The IP core has been successfully synthesized, mapped, simulated and tested on an FPGA evaluation board. The test program that has been written in “C” to evaluate this IP-Core on a Virtex-403 FPGA board yields an encryption throughput of 2.03 Gbps or resource efficiency of 2.126 Mbps/slice.
Key words: Block cipher, FPGA, IP-Core, PRINCE, VHDL, ,
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Cite this Reference:
Yasir Amer Abbas, Razali Jidin, Norziana Jamil, Muhammad Reza Z’aba and Mohd Ezanee Rusli, . PRINCE IP-core on Field Programmable Gate Arrays (FPGA). Research Journal of Applied Sciences, Engineering and Technology, (8): 914-922.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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