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Article Information:
Energy Efficient Multiplexer and De-multiplexer Using FINFET Technology
R. Arunya, S. Ranjith, P. Umarani, A. Ramya and T. Ravi
Corresponding Author: R. Arunya
Submitted: February 3, 2015
Accepted: March 12, 2015
Published: July 20, 2015 |
Abstract:
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This study entirely focused on low power by reducing the switching activities and implemented with the device called FIN Field Effect Transistor. Low power has emerged as a principal theme in today’s world of electronics industries. The invention of the first Integrated Circuitsb (IC) three decades ago, VLSI designers have been looking for methods to speed up digital circuits and to reduce the area for of digital system. However, the evolution of portable system and advanced DSB (Deep Sub-micron) fabrication technologies has brought power dissipation as another critical design factor. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. The proposed DLFF use new clock gating techniques that reduce power dissipation deactivating the clock signals, which consumes less power than the existing DLFF. Here in this study we design an 81 multiplexer, 161 and 18, 116 demultiplexer using 3 bit synchronous counter output as selection lines for this multiplexer and de-multiplexer in MOSFET and FINFET technology.
Key words: Clock gating, DLDFF, FINFET, sequential circuits, , ,
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Cite this Reference:
R. Arunya, S. Ranjith, P. Umarani, A. Ramya and T. Ravi, . Energy Efficient Multiplexer and De-multiplexer Using FINFET Technology. Research Journal of Applied Sciences, Engineering and Technology, (8): 923-931.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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