Abstract

The level shifters play a crucial role in multi supply systems and it is the effective way to reduce the power consumption at system level. The level shifters are the interfacing circuits, used to interface multi supply voltage modules. The design and analysis of competent level shifter is described in this study, with a lower energy and delay constraints. It is a novel architecture with multiplexer based circuit to perform both levels-up and levels-down operations. Proposed level shifter circuit has designed and analyzed using 90 nm CMOS process technology. This proposed level shifter can be operated at different supply voltages from 0.3 to 0.5V of VDDL and 0.9 to 1.1V of VDDH. The experimental and simulation results exhibits that the proposed circuit is having levels-up and levels-down average power is 17.57 nW and delay is 1.49 ns at a simulated frequency of 1 MHz. The level shifter has designed and simulated with different load and operating conditions. The proposed competent level shifter circuit is suitable for low power and high speed applications.

Keywords:

Area efficient, delay, level shifter, low power, multi VDD systems, VLSI,

References

Competing interests

The authors have no competing interests.

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Copyright

The authors have no competing interests.