Research Article | OPEN ACCESS
Bidirectional Virtual Bit-slice Synchronizer: A Scalable Solution for Hardware-level Barrier Synchronization
Jamil Al Azzeh
Department of Computer Engineering, Al Balqa Applied University, Amman, 11134, Jordan
Research Journal of Applied Sciences, Engineering and Technology 2015 8:902-909
Received: June 24, 2015 | Accepted: August 15, 2015 | Published: November 15, 2015
Abstract
In the study, a new distributed hardware-level method for barrier synchronization of parallel processes in a mesh-connected parallel system is presented, which is based on the use of a virtually sliced barrier control network timed by two bidirectional clock pulse waves originating from the corner processors of the mesh.
Keywords:
Barrier synchronization, hardware-level barrier, mesh-connected parallel system, parallel processes,
Competing interests
The authors have no competing interests.
Open Access Policy
This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Copyright
The authors have no competing interests.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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