Abstract

Hardware implementation for decimal operations are more important rather which is more useful in the field of technical (DSP, Microprocessor, Digital Image Processing, etc.) and non-Technical (banking calculation, currency conversion, even in office ledgers, etc.). The main purpose of this research is to improve the speed of the digital processors such as adders, multipliers, which are the prime factors in digital circuits. Here is the architecture of a BCD multiplier, which can increase the efficiency and performance of the digital systems. The binary and decimal numbers are converted to BCD ad then multiplied using Vedic algorithm. High speed multiplier architecture that we designed here is using Vedic mathematics. Urdhva-Tiryagbyham sutra is used to design Vedic multiplier. Power and area are the other paramount of the VLSI design, to diminish that here reversible logic gates are used. The circuit in this study is constructed using Vedic Multiplier with reversible logic gates. Verilog HDL code has been written to perform the simulation. The area and power consumption of Vedic multiplier and Vedic multiplier using reversible logic are calculated using cadence software and both of the results are compared. Vedic multiplier is used in DSP applications such as IIR and FIR filters, FFT and convolution.

Keywords:

BCD, cadence, reversible logic gates, urdhva-triyagbhayam, vedic mathematics, verilog HDL, xilinx,

References

Competing interests

The authors have no competing interests.

Open Access Policy

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Copyright

The authors have no competing interests.