Abstract

The Substitution Box (S-Box) and Inverse MixColumn (Inv MixColumn) forms core building blocks in Advanced Encryption Standard (AES) based Security Algorithm. This study presents full custom design of Composite S-Box by reducing the composite field arithmetic of Multiplication Inverse (MI) and Affine/Inverse Affine Transformation. Design of proposed new MI and Affine/Inverse Affine Transformation techniques are integrated in Composite S-Box of both AES Encryption and Decryption. Very Large Scale Integration (VLSI) System design environment is considered in this research work to measure the performance improvement. High Speed, less area utilization and Lower power consumptions are the important parameter in VLSI System design environment. Hence, the main goal of this research work is to reduce the hardware complexity, Power and Delay consumption of AES Encryption and Decryption process. The principle of reducing the redundant functions is used in both MI and Affine/Inverse Affine Transformation of Proposed Composite S-Box design for reducing the hardware complexity and power consumption. Proposed new Composite S-Box design offers 6.52% reduction of Slices, 5.68% reduction of Look up Tables (LUTs), 2.24% reduction of delay and 6.15% reduction of Power consumption than traditional Composite S-Box design. Further Proposed new composite S-Box design is integrated into both AES encryption and AES decryption process to improve the performance evaluation of AES algorithm.

Keywords:

Advanced Encryption Standard (AES), Affine/Inverse affine transformation, Inverse Mixcolumn, Multiplicative Inverse (MI), Very Large Scale Integration (VLSI),

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Competing interests

The authors have no competing interests.

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