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     Research Journal of Applied Sciences, Engineering and Technology


Implementation and Analysis of Biological Synaptogenesis Technique on Nodes and Interconnects for NoC Fault Tolerance

Muhammad Athar Javed Sethi, Fawnizu Azmadi Hussin and Nor Hisham Hamid
Department of Electrical and Electronic Engineering, Universiti Teknologi PETRONAS, Tronoh, Perak, Malaysia
Research Journal of Applied Sciences, Engineering and Technology  2016  4:483-489
http://dx.doi.org/10.19026/rjaset.12.2388  |  © The Author(s) 2016
Received: September ‎22, ‎2015  |  Accepted: October ‎30, ‎2015  |  Published: February 25, 2016

Abstract

Bio-inspired Network on Chip (NoC) fault tolerant techniques are a novel way of solving the complex faulty situation in NoC. The excessive and parallel communication requirements of heterogeneous Processing Elements (PE’s) in NoC have made the communication structure very complex. The size of the devices are scaled down to support the complexity but the size of interconnects remains the same. Due to this interconnects have contributed to faults. Different fault tolerant techniques have been proposed. But all these conventional algorithms have drawbacks of adaptiveness and robustness. The proposed synaptogensis based bio-inspired technique is based on one of the characteristics of biological brain. This technique is robust as it makes the NoC fault-tolerant and able to reconfigure upon detection of router or interconnect faults. In this study, two techniques based on synaptogensis algorithm have been critically analyzed. In improved algorithm, the packet network latency was reduced to 34.62%, bandwidth was efficiently utilized by 5.03% and throughput was increased by 36.36%. The bio-inspired algorithm has better accepted traffic rate as compared to the traditional fault tolerant technique.

Keywords:

Fault tolerant, Network on Chip (NoC), neuron, Processing Elements (PE, synapse, synaptogenesis,


References

  1. Ben-Itzhak, Y., E. Zahavi, I. Cidon and A. Kolodny, 2012. HNOCS: Modular open-source simulator for heterogeneous NoCs. Proceeding of the International Conference on Embedded Computer Systems (SAMOS), Samos, pp: 51-57.
    CrossRef    
  2. Chang, Y.C., C.T. Chiu, S.Y. Lin and C.K. Liu, 2011. On the design and analysis of fault tolerant NoC architecture using spare routers. Proceeding of the 16th Asia and South Pacific Design Automation Conference. Yokohama, pp: 431-436.
    CrossRef    
  3. Dressler, F. and O.B. Akan, 2010. Bio-inspired networking: From theory to practice. IEEE Commun. Mag., 48(11): 176-183.
    CrossRef    
  4. Hashmi, A., H. Berry, O. Temam and M. Lipasti, 2011. Automatic abstraction and fault tolerance in cortical microachitectures. Proceeding of the 38th Annual International Symposium on Computer Architecture (ISCA, 2011), San Jose, CA, pp: 1-10.
    CrossRef    
  5. Kim, Y.B. and Y.B. Kim, 2007. Fault tolerant source routing for network-on-chip. Proceeding of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'07), Rome, pp: 12-20.
    CrossRef    
  6. Koibuchi, M., H. Matsutani, H. Amano and T.M. Pinkston, 2008. A lightweight fault-tolerant mechanism for network-on-chip. Proceeding of the 2nd ACM/IEEE International Symposium on Networks-on-Chip. Newcastle upon Tyne, pp: 13-22.
    CrossRef    
  7. Lehtonen, T., D. Wolpert, P. Liljeberg, J. Plosila and P. Ampadu, 2010. Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE T. VLSI Syst., 18(4): 527-540.
    CrossRef    
  8. Nicopoulos, C., V. Narayanan and C.R. Das, 2009. Network-on-chip architectures: A holistic design exploration. Lecture Notes in Electrical Engineering, Springer, Dordrecht, New York, Vol. 45.
    CrossRef    
  9. Nunez-Yanez, J.L., D. Edwards and A.M. Coppola, 2008. Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Comput. Digit. Tec., 2(3): 184-198.
    CrossRef    
  10. Pasricha, S. and Y. Zou, 2011. A low overhead fault tolerant routing scheme for 3D networks-on-chip. Proceeding of the 12th International Symposium on Quality Electronic Design (ISQED, 2011). Santa Clara, CA, pp: 1-8.
  11. Rantala, V., T. Lehtonen and J. Plosila, 2006. Network on chip routing algorithms. TUCS Technical Report, No. 779.
  12. Rosenzweig, M.R., S.M. Breedlove and N.V. Watson, 2005. Biological Psychology: An Introduction to Behavioral and Cognitive Neuroscience. 4th Edn., Sinauer Associates Publisher, Sunderland, Mass.
  13. Schonwald, T., J. Zimmermann, O. Bringmann and W. Rosenstiel, 2007. Fully adaptive fault-tolerant routing algorithm for network-on-chip architectures. Proceeding of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD, 2007). Lubeck, pp: 527-534.
    CrossRef    
  14. Sethi, M.A.J., F.A. Hussin and N.H. Hamid, 2013a. Implementation of biological sprouting algorithm for NoC fault tolerance. Proceeding of the IEEE International Conference on Circuits and Systems (ICCAS, 2013), pp: 39-44.
    CrossRef    
  15. Sethi, M.A.J., F.A. Hussin and N.H. Hamid, 2013b. Synaptogenesis based bio-inspired NoC fault tolerant interconnects. Proceeding of the IEEE International Conference on Control System, Computing and Engineering (ICCSCE, 2013), pp: 46-51.
    CrossRef    
  16. Sethi, M.A.J., F.A. Hussin and N.H. Hamid, 2014. Bio-inspired NoC fault tolerant techniques. Proceeding of the 5th International Conference on, 2014Intelligent and Advanced Systems (ICIAS, 2014), pp: 1-6.
    CrossRef    
  17. Sethi, M.A.J., F.A. Hussin and N.H. Hamid, 2015. Survey of network on chip architectures. Parameters, 1: 5-113.
  18. Wu, J., 2000. A fault-tolerant adaptive and minimal routing approach in n-D meshes. Proceeding of the International Conference on Parallel Processing. Toronto, Ont., pp: 431-438.
  19. Zhu, H., P.P. Pande and C. Grecu, 2007. Performance evaluation of adaptive routing algorithms for achieving fault tolerance in NoC fabrics. Proceeding of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP’2007). Montreal, Que., pp: 42-47.
    CrossRef    

Competing interests

The authors have no competing interests.

Open Access Policy

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Copyright

The authors have no competing interests.

ISSN (Online):  2040-7467
ISSN (Print):   2040-7459
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