Abstract

Due to acceptance of the portable system with fast growth of power density in the integrated circuits, the power dissipation and the performance is considered while the system is designed. The main goal of the VLSI design is to design the adders in more efficient way. By that way the Carry Select Adder (CSLA) is an adder designed, which computes n+1 bit sum of two n bit numbers. In this study Modified 16-b SQRT with Modified Area efficient CSLA is proposed. From the design of Modified Area Efficient CSLA it is experiential that there is an option of reducing the area more and consumes low power when compared with Regular CSLA. Modified Area Efficient CSLA (MA-CSLA) utilizes BEC which reduces the area more and the total gate count is also gets condensed. The proposed study makes use of a simple and well-organized gate-level alteration to considerably reduce the area and power of the CSLA. By the support of alteration 8-, 16-, 32- and 64-b, respectively Square-Root CSLA (SQRT CSLA) model have been evolved and evaluated with the regular SQRT CSLA model. This study estimates the performance of the proposed designs in terms of delay, area and power. The results analysis shows that the proposed Modified Area Efficient CSLA structure is better than the regular SQRT CSLA.

Keywords:

Area-efficient, Carry Select Adder (CSLA), delay, modified area efficient CSLA,

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Competing interests

The authors have no competing interests.

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