Abstract

The aim of this exploration paper is to approve the Advanced Extensible Interface Bus Protocol utilizing Randomized Verilog Environment. System on-Chip (SOC) design and verification has turned out to be more perplexing. Step by step instructions to verify a configuration has adequately has turned into a challenge. In this study, how to develop the verification Environment of AXI using Verilog HDL and Randomization is presented. The Design under Test (DUT) AXI bus is elaborated, followed by a comprehensive analysis of the verification plan has been made according to the protocol. Integrated verification environment with Functional coverage and constrained arbitrary vectors generation is executed. With this environment, more coverage and minimized time spending verification has been accomplished. AXI or the Advance Extensible Interface is a development of AMBA interface characterized in the AMBA 3 specification. It is focused for high performance and high clock frequency system designs and incorporates qualities to make it suitable for fast sub-micron interconnects. AXI underpins a whole lot of features such as separate address/control and data phases, keeping up unaligned data transfers utilizing byte strobes, burst based transactions through scarcely start address issued, issuing of various addresses without of order response and simple adding of register stages to present timing closure.

Keywords:

AMBA, , AXI protocol , channel, SOC,

References

1. ARM Limited, Year. AMBA AXI Protocol Specification Version 2.0. ARM Limited.
   
2. ARM Limited, 2004. PrimeCell AXI Configurable Interconnect (PL300). Revision: r0p1. Technical Reference Manual. ARM Limited, Retrieved from: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0354b/DDI0354.Pdf.
   Direct Link
3. ARM Limited, 2007. AMBA Design Kit Technical Reference Manual. Revision: r3p0, ARM Limited, Retrieved from: http://infocenter.arm.com/help/index.jsp?Topic=/com.arm.doc.ddi0243c/index.html.
   Direct Link
4. Bergeron, J., 2003. Writing Testbenches: Functional Verification of HDL Models. Kluwer Academic Publishers, Springer, US.
   CrossRef    
5. Brown, S.D. and Z.G. Vranesic, 2000. Fundamentals of Digital Logic with VHDL Design. McGraw-Hill, Boston.
   
6. Pradeep, S.R. and C. Laxmi, 2014. Design and verification environment for Amba Axi protocol for Soc integration. Int. J. Res. Eng. Technol., 3(3): 338-343.
   
7. Ranga, A., L. Hari Venkatesh and Venkanna, 2012. Design and implementation of AMBA-AXI protocol using VHDL for Soc integration. Int. J. Eng. Res. Appl., 2(4): 1102-1106.
   
8. Spear, C., 2008. SystemVerilog for Verification: A Guide to Learning the Testbench Language Features. Springer, New York.
   

Competing interests

The authors have no competing interests.

Open Access Policy

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Copyright

The authors have no competing interests.