Abstract
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Article Information:
Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern
S. Saravanan and Har Narayan Upadhyay
Corresponding Author: S. Saravanan
Submitted: April 17, 2012
Accepted: May 06, 2012
Published: November 15, 2012 |
Abstract:
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Aim of this study is to focus on reducing test pattern with effective Linear Feedback Shift
Register (LFSR) reseeding. Test data volume of modern devices for testing increases rapidly corresponding
to the size and complexity of the Systems-on-Chip (SoC). LFSR is a good pseudorandom pattern generator,
which generates all possible test vectors with the help of the tap sequence. It can achieve high fault
coverage by reducing correlation between the test vectors. Reseeding is a powerful method for reducing the
test data volume and storage. This study presents a new LFSR reseeding technique for efficient reduction of
test pattern. A new encoding technique is proposed in this study which is used to reduce the size of the test
data. Size of the test data can be reduced by LFSR clock which is inactive for several clock cycles after the
input seed is given. When the clock goes to inactive state, a rotate right shift operation is done on the seed
to get all the remaining possible values. After getting all the possible values for that seed a new seed is
given by making the clock active. Test data volume is reduced by storing the data only when the clock is
active. With in the reduced clocks, rest of all the remaining test vectors was derived. A special Control
logic is used to make the clock active as well as inactive. Experimental results are targeted to ISCAS89
benchmark circuits.
Key words: Clock active and inactive , control logic, encoding, linear feedback shift register reseeding, , ,
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Cite this Reference:
S. Saravanan and Har Narayan Upadhyay, . Effective LFSR Reseeding Technique for Achieving Reduced Test Pattern. Research Journal of Applied Sciences, Engineering and Technology, (22): 4783-4786.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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