Research Article | OPEN ACCESS
Design and Implementation of Low Power AES SBOX with Error Detection Circuit
1V. Devendiran and 2S. Letitia
1Faculty of Information and Communication Engineering, Anna University, Chennai, India
2Department of ECE, Thanthai Periyar Government Institute of Technology, Vellore, India
Research Journal of Applied Sciences, Engineering and Technology 2015 7:824-830
Received: February 24, 2015 | Accepted: April 2, 2015 | Published: July 10, 2015
Abstract
Soft error is nowadays a serious problem when implementing AES SBOX algorithms in hardware. The objective of the study is to detect the error using parity bit for the AES SBOX and implementation in hardware with low area and power. This circuit can products the AES Encryption/Decryption process and systems against fault based attacks. It can also apply to any digital communication systems and security related applications.
Keywords:
AES SBOX, error detection , low area,
Competing interests
The authors have no competing interests.
Open Access Policy
This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Copyright
The authors have no competing interests.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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