Abstract

In this study, an optimized Direct Digital Frequency Synthesizer (DDFS) utilizing Piecewise Linear Approximation is introduced. The proposed technique allows successive read access to memory cells per one clock cycle using time sharing. The output values will be temporarily stored and read at a later time. The output of this system is a reconstructed signal that is a good approximation of the desired waveform. As a result, the DDFS only needs to store fewer coefficients and the hardware complexity is significantly reduced. The proposed DDFS has been analyzed using MATLAB. The SFDR of synthesized achieved is 84.2 dBc. To prove the better performance of proposed DDS architecture it is compared favorably with several existing DDS architectures. In future it can also be used to improve the performance of Hybrid DDS-PLL Synthesizers.

Keywords:

DDFS, frequency synthesis, ROM and piecewise linear approximation,

References

Competing interests

The authors have no competing interests.

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Copyright

The authors have no competing interests.