Abstract

Most modern computers use the 2’s complement system to represent negative numbers and to perform subtraction by using adder circuit. Several criteria such as speed, power consumption and propagation delay must be taken into account in the design of arithmetic circuits. This study proposed a technique to build an improved 2’s complement adder circuit using the combination of existing XOR and new full adder structure. The design is implemented in CEDEC 0.18 μm CMOS process at 3.3v supply voltage. The results showed that the circuit is required only 0.83nW with maximum delay of 50.08 ns for 1-bit adder. Delay and power dissipation of different adder circuits for various numbers of inputs are also simulated and analyzed. Comparison study showed that the design is given a better critical delay and low power dissipation compared to other research studies. Moreover, because of using less number of transistors, the design occupied small die area. The compact size of the circuit with low power and low propagation delay is highly required in arithmetic circuits.

Keywords:

CMOS, full adder, 2, PTL, PDP, XOR,

References

Competing interests

The authors have no competing interests.

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Copyright

The authors have no competing interests.