Research Article | OPEN ACCESS
Object Oriented Model for Evaluation of On-Chip Networks
1Sheraz Anjum, 1Ehsan Ullah Munir, 2Waqas Anwar and 3Nadeem Javaid
1COMSATS Institute of Information Technology, Wah Cantt, Pakistan
2COMSATS Institute of Information Technology, Abbottabad, Pakistan
3COMSATS Institute of Information Technology, Islamabad, Pakistan
Research Journal of Applied Sciences, Engineering and Technology 2013 2:353-356
Received: April 08, 2012 | Accepted: April 30, 2012 | Published: January 11, 2013
Abstract
The Network on Chip (NoC) paradigm is rapidly replacing bus based System on Chip (SoC) designs due to their inherent disadvantages such as non-scalability, saturation and congestion. Currently very few tools are available for the simulation and evaluation of on-chip architectures. This study proposes a generic object oriented model for performance evaluation of on-chip interconnect architectures and algorithms. The generic nature of the proposed model can help the researchers in evaluation of any kind of on-chip switching networks. The model was applied on 2D-Mesh and 2D-Diagonal-Mesh on-chip switching networks for verification and selection of best out of both the analyzed architectures. The results show the superiority of 2D-Diagonal-Mesh over 2D-Mesh in terms of average packet delay.
Keywords:
2D-diagonal-mesh, network simulator-2, networks on chip, object oriented model, traffic models,
Competing interests
The authors have no competing interests.
Open Access Policy
This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Copyright
The authors have no competing interests.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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