Abstract

This study presents a Fault Tolerant memory cores based on the property of Component Reusability, a method for Fault Tolerance for content addressable memories. The memories used in the design are 256, 512, 1024 and 2048 bytes. The fault is injected into the circuitry operation by using Automatic Test Pattern Generators (ATPGs). The design has been implemented in Cadence 90 nm technology and tested with Fault Injection Circuits and ATPG effectiveness was found out to be 100% at a frequency of 500 MHZ.

Keywords:

ATPG, BIST, fault tolerant, LFSR, magnetic memories,

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Competing interests

The authors have no competing interests.

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