Research Article | OPEN ACCESS
Implementation of High Speed FIR Filter: Performance Comparison with Different Parallel Prefix Adders in FPGAs
R. Uma and P. Dhavachelvan
Department of Computer Science, School of Engineering, Pondicherry University, Puducherry, India
Research Journal of Applied Sciences, Engineering and Technology 2014 13:2705-2710
Received: September 04, 2013 | Accepted: September 27, 2013 | Published: April 05, 2014
Abstract
This study describes the design of high speed FIR filter using parallel prefix adders and factorized multiplier. The fundamental component in constructing any high speed FIR filter consists of adders, multipliers and delay elements. To meet the constraint of high speed performance and low power consumption parallel prefix adders are more suitable. This study focus the design of new Parallel Prefix Adder (PPA) and new multiplier cell called factorized multiplier with minimal depth algorithm and its functional characteristics is compared with the existing architecture in terms of delay and area. The performance evaluation of the proposed PPA and multiplier are examined for the bit sizes of 8, 16, 32 and 64. The coefficient of the filter is obtained through hamming window using MATLAB program. The proposed FIR filter using new PPA and factorized multiplier has been prototyped on XC3S1600EFG320 in Spartan-3E Platform using Integrated Synthesis Environment (ISE) for 90 nm process. Nearly 14% of slice utilization and 34% of speed improvement has been obtained for FIR using new PPA and factorized multiplier.
Keywords:
Delay element, factored multiplier, FIR filter, parallel prefix adders, signal processing,
References
-
Baugh, C. and B.A. Wooly, 1973. A two's complementary parallel array multiplication algorithm. IEEE T. Comput., C-22(12): 1045-1047.
CrossRef
-
Ching, Y.N., 2005. Low-power high-speed multipliers. IEEE T. Comput., 54(3): 355-361.
-
Han, T. and D. Carlson, 1987. Fast area efficient VLSI adders. Proceedings of the 8th Symposium on Computer Arithmetic, pp: 49-56.
CrossRef
-
Jiang, X. and Y. Bao, 2010. FIR filter design based on FPGA. Proceeding of International Conference on Computer Application and System Modeling, (ICCASM 2010).
-
Knowles, S., 2001. A family of adders. Proceeding of the 15th IEEE Symposium on Computer Arithmetic, pp: 277-281.
CrossRef
-
Kogge, P.M. and H.S. Stone, 1973. A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE T. Comput., 22(8): 786-793.
CrossRef
-
Patel, R.A. and S. Boussakta, 2007. Fast parallel-prefix architectures for modulo 2n-1 addition with a single representation of zero. IEEE T. Comput., 56(11): 1484-1492.
CrossRef
-
Richard, P.B., 1982. A regular layout for parallel adders. IEEE T. Comput., c-31(3): 260-264.
-
Richard, E.L. and M.J. Fischer, 1980. Parallel prefix computation. J. Assoc. Comput. Mach., 27(4): 831-838.
CrossRef
-
Sabyasachi, D. and S.P. Khatri, 2008. A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic. IEEE T. VLSI Syst., 16(3).
-
Sheplie, M., 2004. High performance array multiplier. IEEE T. VLSI Syst., 12(3): 320-325.
-
Sklansky, J., 1960. Conditional-sum addition logic. IRE T. Electron. Comput., EC-9(2): 226-231.
CrossRef
-
Uma, R., V. Vijayan, M. Mohanapriya and S. Paul, 2012. Area, delay and power comparison of adder topologies. Int. J. VLSI Design Commun. Syst., 3(1): 153.
CrossRef
-
Wallace, C.S., 1964. A suggestion for a fast multiplier. IEEE T. Comput., 13: 14-17.
CrossRef
-
Wei, L., R.J. Yang and X.T. Cui, 2008. Design of FIR filter based on distributed arithmetic and its FPGA implementation. Chinese J. Sci. Instrum., 29: 2100-2104.
Competing interests
The authors have no competing interests.
Open Access Policy
This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Copyright
The authors have no competing interests.
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ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
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