Abstract

Advanced Encryption Standard is one of the most successful techniques used in various security applications. The AES technique is known to provide reliable security standards, which is why it is preferred over many other methods. The AES architecture consists of S-Box, Shift-Rows, Mix-Columns and Add Round key. Improving the S-Box structure using pipelining improves the speed of operations along with the security. The main aim of this research study is to design a modified composite S-Box for low area, power and high Speed with high security for application in AES process. In this study, we propose a WPT in S-Box also controlling the registers with a clock-gate structure, to further reduce the operational delay and obtain high security. The modified S-Box is then included in the AES architecture with an additional modification on the overall AES architecture by introducing the WPT in every round of AES operation. This is not only improves the speed of operation and also it provides high security compared to many existing techniques along with the area and power reduction. Simulations have been performed in the ModelSim6.3c and Synthesis is carried out using Xilinx10.1.

Keywords:

AES, , modified S-box, Wave Pipelined Technique (WPT) , xilinx,

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Competing interests

The authors have no competing interests.

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The authors have no competing interests.