Abstract

Multiplication and Accumulation (MAC) unit is recognized as high potential in every Digital Signal Processor (DSP). In MAC unit, both Multiplication and Accumulation functions are involved, but the performances of MAC unit is mostly depends on dataflow structure of Accumulation unit. In this study, Modified Square Root Carry Select Adder (MSQRTCSLA) is designed through Very Large Scale Integration (VLSI) System design environment. In the proposed design, Half Adder (HA) and Full Adder (FA) circuits are realized and identified the redundant logic functions. Hence, a new half adder named “Reduced Half Adder (RHA)” and a new full adder named “Reduced Full Adder (RFA)” are proposed in this study. Further the design of RHA and RFA is integrated into Binary to Excess-1 Converter (BEC) based SQRT CSLA architecture to improve the accumulation function of MAC unit. A new BEC based SQRT CSLA architecture is named as “Modified Square Root Carry Select Adder (MSQRTCSLA). Low power consumption, High Speed and Less area utilization are the main key factors in VLSI System design environment. Therefore, Minimizing the Area-Delay Product (ADP) of MSQRTCSLA is the main goal of this study. MSQRTCSLA based accumulation structure offers 22.86% reduction of delay and 8.87% reduction power consumption than conventional BEC based SQRT CSLA based accumulation structure.

Keywords:

Binary to Excess 1 Converter (BEC) based Square Root Carry Select Adder (SQRT CSLA), Modified Square Root Carry Select Adder (MSQRTCSLA), Reduced Full Adder (RFA), Reduced Half Adder (RHA), Very Large Scale Integration (VLSI) system design environment,

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Competing interests

The authors have no competing interests.

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