|
Abstract
|
Article Information:
Optimized Nanometric Fault Tolerant Reversible BCD Adder
Majid Haghparast and Masoumeh Shams
Corresponding Author: Majid Haghparast
Submitted: October 31, 2011
Accepted: December 09, 2011
Published: May 01, 2012 |
Abstract:
|
In this study a novel nanometric fault tolerant quantum and reversible binary coded decimal adder
is proposed. Reversible logic has found emerging attentions in optical information processing, quantum
computing, nanotechnology and low power design. BCD Adder is a combinational circuit that can be used for
the addition of two numbers in BCD arithmetic's. The proposed reversible BCD adder has also parity preserving
property. It is better than all the existing counterparts. The proposed circuit is optimized. It is compared with
the existing circuits in terms of number of constant inputs, number of garbage outputs, quantum cost and
hardware complexity. All of the parameters are improved dramatically. It is to be noted that all the circuits have
nanometric scales.
Key words: Binary coded decimal adder, fault tolerant, nanotechnology based systems, nanometric circuits, quantum computing, quantum circuits, quantum gates
|
|
Abstract
|
PDF
|
HTML |
|
Cite this Reference:
Majid Haghparast and Masoumeh Shams, . Optimized Nanometric Fault Tolerant Reversible BCD Adder. Research Journal of Applied Sciences, Engineering and Technology, (09): 1067-1072.
|
|
|
|
 |
ISSN (Online): 2040-7467
ISSN (Print): 2040-7459 |
 |
| Information |
|
|
|
|
| Sales & Services |
|
|
|
|
