Abstract

This study entirely focused on low power by reducing the switching activities and implemented with the device called FIN Field Effect Transistor. Low power has emerged as a principal theme in today’s world of electronics industries. The invention of the first Integrated Circuitsb (IC) three decades ago, VLSI designers have been looking for methods to speed up digital circuits and to reduce the area for of digital system. However, the evolution of portable system and advanced DSB (Deep Sub-micron) fabrication technologies has brought power dissipation as another critical design factor. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. The proposed DLFF use new clock gating techniques that reduce power dissipation deactivating the clock signals, which consumes less power than the existing DLFF. Here in this study we design an 8×1 multiplexer, 16×1 and 1×8, 1×16 demultiplexer using 3 bit synchronous counter output as selection lines for this multiplexer and de-multiplexer in MOSFET and FINFET technology.

Keywords:

Clock gating , DLDFF , FINFET , sequential circuits,

References

Competing interests

The authors have no competing interests.

Open Access Policy

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Copyright

The authors have no competing interests.