Abstract

The Advanced Encryption Standard (AES) is the symmetric cryptography standard that can be used to protect the electronic data. The natural and malicious injected faults may cause confidential information leakage and also reduce its reliability. In this study, we have explained a low complexity fault detection schemes for the AES architecture. The proposed work is low-complexity fault detection schemes using composite fields in polynomial basis for the AES encryption and decryption. These schemes are independent of the existing S-box and inverse S-box constructed. Here we have developed a new technique for the fault detection of subbyte and inverse subbyte using multiplicative inversion and affine transformation of the S-box and the inverse S-box. These are constructed in S-box and the inverse S-box. So this scheme can be used for the S-boxes and the inverse S-boxes in composite fields subbyte and inverse subbyte and using ROM. The proposed AES Fault detection scheme is coded in VHDL (Very High Speed Integrated Circuits Hardware Description Language), synthesized and simulated using EDA (Electronic Design Automation) tool-XilinxISEVirtex FPGA (http://www.xilinx.com/.). Finally the results are compared with Conventional ROM based subbyte and inverse subbyte to show the significant improvement in its efficiency in terms of path delay, speed and area.

Keywords:

Advanced Encryption Standard (AES), composite field, decryption, encryption, fault detection, polynomial basis , S-box,

References

1. Bertoni, G., L. Breveglieri, I. Koren, P. Maistri and V. Piuri, 2002. A parity code based fault detection for an implementation of the advanced encryption standard. Proceeding of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT, 2002), pp: 51-59.
   CrossRef    
2. Bertoni, G., L. Breveglieri, I. Koren, P. Maistri and V. Piuri, 2003. Error analysis and detection procedures for a hardware implementation of the advanced encryption standard. IEEE T. Comput., 52(4): 492-505.
   CrossRef    
3. Breveglieri, L., I. Koren and P. Maistri, 2007. An operation-centered approach to fault detection in symmetric cryptography ciphers. IEEE T. Comput., C-56(5): 534-540.
   CrossRef    
4. Canright, D., 2005. A very compact S-box for AES. In: Rao, J.R. and B. Sunar (Eds.), CHES, 2005. LNCS 3659, Springer, Berlin, Heidelberg, pp: 441-455.
   CrossRef    
5. Cohen, A.E., 2007. Architectures for cryptography accelerators. Ph.D. Thesis, University of Minnesota, Twin Cities.
   
6. Karpovsky, M.G., K.J. Kulikowski and A. Taubin, 2004. Differential fault analysis attack resistant architectures for the advanced encryption standard. In: Quisquater, J.J., P. Paradinas, Y. Deswarte and A.A. El Kalam (Eds.), Smart Card Research and Advanced Applications VI (CARDIS, 2004). Kluwer Academic Publishers, Amsterdam, 153: 177-192.
   CrossRef    
7. Karri, R., P. Mishra, K. Wu and K. Yongkook, 2001. Fault-based side-channel cryptanalysis tolerant Rijndael symmetric block cipher architecture. Proceeding of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT, 2001), pp: 418-426.
   CrossRef    
8. Karri, R., P. Mishra, K. Wu and Y. Kim, 2002. Concurrent error detection schemes for fault-based side-channel cryptanalysis of symmetric block ciphers. IEEE T. Comput. Aid. D., 21(12): 1509-1517.
   CrossRef    
9. Kermani, M.M. and A. Reyhani-Masoleh, 2006. Parity-based fault detection architecture of S-box for advanced encryption standard. Proceeding of the IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT, 2006), pp: 572-580.
   
10. Maistri, P. and R. Leveugle, 2008. Double-data-rate computation as a countermeasure against fault analysis. IEEE T. Comput., 57(11): 1528-1539.
    CrossRef    
11. Mentens, N., L. Batina, B. Preneel and I. Verbauwhede, 2005. A systematic evaluation of compact hardware implementations for the Rijndael S-box. Proceeding of the Cryptographers’ Track at the RSA Conference (CT-RSA, 2005), pp: 323-333.
    
12. Moratelli, C., F. Ghellar, E. Cota and M. Lubaszewski, 2008. A fault-tolerant, DFA-resistant AES core. Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS, 2008), pp: 244-247.
    
13. Mozaffari-Kermani, M. and A. Reyhani-Masoleh, 2008. A lightweight concurrent fault detection scheme for the AES S-boxes using normal basis. Proceeding of the International Workshop Cryptographic Hardware and Embedded Systems (CHES '08), pp: 113-129.
    CrossRef    
14. National Institute of Standards and Technologies (NIST), 2001. Announcing the Advanced Encryption Standard (AES). FIPS Publication 197, National Institute of Standards and Technologies, Washington, DC, pp: 51.
    
15. Rijmen, V., 2000. Efficient implementation of the Rijndael S-box. Department of ESAT, Katholieke Universiteit Leuven, Leuven, Belgium.
    
16. Satoh, A., S. Morioka, K. Takano and S. Munetoh, 2001. A compact Rijndael hardware architecture with S-box optimization. Proceeding of the 7th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology (ASIACRYPT, 2001), pp: 239-254.
    
17. Satoh, A., T. Sugawara, N. Homma and T. Aoki, 2008. High-performance concurrent error detection scheme for AES hardware. Proceeding of the CHES, pp: 100-112.
    CrossRef    
18. Wolkerstorfer, J., E. Oswald and M. Lamberger, 2002. An ASIC implementation of the AES S-boxes. In: Preneel, B. (Ed.), CT-RSA, 2002. LNCS 2271, Springer-Verlag, Berlin, Heidelberg pp: 67-78.
    
19. Wu, S.Y. and H.T. Yen, 2006. On the S-box architectures with concurrent error detection for the advanced encryption standard. IEICE T. Fund. Electr., E89-A(10): 2583-2588.
    CrossRef    
20. Yen, C.H. and B.F. Wu, 2006. Simple error detection methods for hardware implementation of advanced encryption standard. IEEE T. Comput., 55(6): 720-731.
    CrossRef    
21. Zhang, X. and K.K. Parhi, 2004. High-speed VLSI architectures for the AES algorithm. IEEE T. VLSI Syst., 12(9): 957-967.
    CrossRef    
22. Zhang, X. and K.K. Parhi, 2006. On the optimum constructions of composite field for the AES algorithm. IEEE T. Circuits-II, 53(10): 1153-1157.
    

Competing interests

The authors have no competing interests.

Open Access Policy

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Copyright

The authors have no competing interests.