Abstract

In this study, we propose a P-type energy recovery logic named as 2P-2P2N to reduce the leakage dissipations in nanometer CMOS processes with gate oxide materials. A combinational circuit 4-bit carry look-ahead adder and a sequential circuit D flip-flop are realized. Near threshold techniques are used to reduce their power dissipations. All the circuits are simulated by HSPICE using 65 nm PTM technology. The results show that the 2P-2P2N circuits adopting near threshold techniques consume about 82.9-88.4% less power than conventional static CMOS logic and about 45.6-53.2% less power than 2N-2N2P adiabatic logic.

Keywords:

2P-2P2N, adiabatic circuits, leakage power, low power, near-threshold techniques,

References

Competing interests

The authors have no competing interests.

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Copyright

The authors have no competing interests.