Abstract

Digital to (DAC) is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp) circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 μm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 μm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.

Keywords:

CMOS, DAC, op-amp, weighted resistor,

References

Competing interests

The authors have no competing interests.

Open Access Policy

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Copyright

The authors have no competing interests.