Abstract

Digital signal transmission analyzer is mainly used for testing the transmission quality of digital communications signal and it usually composed of digital signal generator, pseudo-random signal generator, low-pass filter and digital signal analysis circuit. This study adopts FPGA to implement the digital signal generator and pseudo-random signal generator, as well as to implement the shift register to generate the required M sequence. By changing the low-pass filter cutoff frequency and the amplitude of the pseudo-random signal to analog transmission environment and signal analysis portion consists of the digital signal analysis circuit. The digital signal analysis module extracts the sync signal and produces synchronization scan signal by using the synchronous clock, as the outside trigger signal of oscilloscope to display the eye diagram of the digital signal stably. To analyze the degree of interference and the strength of inter-symbol interference by observing the eye diagram, thus this study implements the performance test for digital signal transmission.

Keywords:

DSP builder, eye diagram, FPGA, low-pass filter, M sequence,

References

Competing interests

The authors have no competing interests.

Open Access Policy

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Copyright

The authors have no competing interests.