Abstract

Flip flops form an indispensable building block in the design of digital systems. In this study, adiabatic switching technique is used in the design of low-power negative edge triggered energy recovery flip-flops. In particular, the negative edge triggered D, SR and JK flip-flop designs based on the Quasi-adiabatic ECRL (Efficient Charge Recovery Logic) architecture are proposed. The projected design is illustrated with an 8 bit Serial Input and Parallel Output shift register (SIPO). The setup time and hold time are minimal in negative edge triggering compared to the pulsed and positive edge triggering which contributes to the high performance and the signal integrity of the design. Additionally, glitching is avoided due to the edge triggering which in turn reduces the soft error rate in the flip-flops. The simulation results have shown improvements in power efficiency by 95 and 75%, respectively for the D flip-flop and 8 bit shift registers than their CMOS counter parts. Due to its several merits, this design can find many real time applications such as digital communication (cryptography), memories and shift registers in microcontrollers. The four phase power clocks are utilized in the pipelining of the stages of the shift register, which mitigates all the relevant timing problems addressed in the literature of flip flops. For simulation, SPICE EDA simulation environment using the 350 nm process technology library from Austria micro systems have been used.

Keywords:

8-bit SIPO register, D flip-flop, efficient charge recovery logic, JK flip-flop, negative edge triggered flip-flops, SR flip-flop,

References

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Competing interests

The authors have no competing interests.

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The authors have no competing interests.