Abstract

Carry Select Adder (CSLA) is one of the high speed adders used in many computational systems to perform fast arithmetic operations. When compared to earlier Ripple Carry Adder and Carry Look Ahead Adder, Regular CSLA (R-CSLA) is observed to provide optimized results in terms of area. This study proposes an efficient method which replaces the RCA using BEC. The modified CSLA architecture has been developed using gate-level modification to significantly reduce the delay and power of the CSLA. Based on this modification 8-, 16-, 32-, 64- and 128-bit Square-Root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design for 256-bit has reduced power and delay as compared with the regular SQRT CSLA. Designs were developed using structural Verilog module and synthesized using Xilinx ISE simulator and the implementation is done in cadence RTL compiler using 0.18 μm technology. For 256-bit addition in this study, it is proposed to simple gate level modification which significantly reduces the power by 19.4% when compared with R-CSLA. The result analysis shows that the proposed architecture achieves two folded advantages in terms of delay and power.

Keywords:

BEC , cadence , CSLA,

References

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Competing interests

The authors have no competing interests.

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The authors have no competing interests.