Abstract

The study was conducted on the analysis of how the nonlinear behavior of the transistor affecting the drain efficiency could be minimized by integrating it in the output matching network of the power amplifier. In wireless communication, higher switching ability power amplifiers are a good choice for future advanced transmitters design. Minimizing all parasitic components is particularly very critical during the design of high-efficiency Switch-Mode Power Amplifiers (SMPA). To use the transistor in switching mode more efficiently, we analyzed some of the dominant parasitic components for better power performance of the transistor. Based on the proposed transistor model, a SMPA based on simplified class F architecture at 5.8 GHz using a Gallium Nitride High Electron Mobility Transistor (GaN HEMT) with the maximum output power of 47 dBm and high performance values of the PAE of 53.9% at peak with the power gain of 12 dB was designed. Load pull technique is used to find out the best load impedance of the amplifier.

Keywords:

Class F, drain efficiency , load-pull, on-resistance, parasitic , switching mode , transistor parasitic,

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Competing interests

The authors have no competing interests.

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