Research Article | OPEN ACCESS
Low Power and Efficient Dadda Multiplier
S. Ravi, Govind Shaji Nair, Rajeev Narayan and Harish M. Kittur
School of Electronics Engineering, VIT University, Vellore, Tamilnadu 632014, India
Research Journal of Applied Sciences, Engineering and Technology 2015 1:53-57
Received: November 13, 2014 | Accepted: November 13, 2014 | Published: January 05, 2015
Abstract
In this study an area optimized Dadda multiplier with a data aware Brent Kung adder in the final addition stage of the Dadda algorithm for improved efficiency has been described in 45 nm technology. Currently the trend is to shift towards low area designs due to the increasing cost of scaled CMOS. An area reduced full adder is the key component in our design. It uses lesser number of gates than conventional design and hence lesser area and delay. The data aware Brent Kung adder in the final addition stage helps in reducing dynamic power as it reduces switching activity depending on the inputs. We have compared the results to the existing benchmark designs and our experimental results show that we have been capable of reducing the area by 13.011% and total power by 26.1% with only a slight increase in the delay.
Keywords:
Brent Kung adder, dadda multiplier, data aware, low area,
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Competing interests
The authors have no competing interests.
Open Access Policy
This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
Copyright
The authors have no competing interests.
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