Abstract

In Digital Signal Processing, Finite Impulse Response (FIR) filter is mostly used for communications and radar applications. The Performance of FIR filter depends on Multiplier and adder circuits used in filter. To reduce the dynamic power consumption and chip size, different multiplier and adder combinations are used in order to improve the overall performance of FIR filter. The Low Power Modified Square Root Carry Select Adder (M-SQRT CSLA) is presented in this study by introducing half adders instead of full adders. The proposed M-SQRT CSLA has been designed to reduce dynamic power consumption. Hence the modified SQRT CSLA is applied into Wallace multiplier for addition process after the partial product generation stage. MAC unit of the Digital FIR filter is designed by using modified Wallace multipliers and M-SQRT CSLA. Further the Group 2, Group 3; Group 4 and Group5 structures of SQRT CSLA were constructed using half adders only. Comparison between proposed SQRT CSLA and Modified Carry Save Adder (MCSA) has been done with reference to the Area, Power and Delay. It is proved that the proposed SQRT CSLA consumes less area and power than all other methods. Simulation is performed by Modelsim6.3c and Synthesis process is done by Xilinx 10.1. The simulation result shows that digital filter with proposed SQRT CSLA occupies less area and consumes low power.

Keywords:

Digital FIR filter , DSP , MAC unit , MCSA , Modified SQRT CSLA,

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Competing interests

The authors have no competing interests.

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