Abstract

In this study, analytical model and electrical equivalent circuit of Through Silicon Via (TSV) is analyzed. Through silicon Vias form an integral component of the 3-D IC technology by enabling vertical interconnections in 3-D ICs. Among various types, the performances of the simplified lumped TSV model of cylindrical and co-axial type were studied. The performance analyses of these structures were presented by introducing these structures between the tiers of digital circuits. The power consumption of the transistor level digital circuits for single tier without TSV and multiple tiers with cylindrical TSV and Co-axial TSV was simulated using Virtuoso Schematic Editor of Cadence. The comparison for cylindrical and co-axial TSV model with different level tiers were tabulated and performed.

Keywords:

Three-dimensional ICs, Through Silicon Via (TSV), TSV lumped RLC model,

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Competing interests

The authors have no competing interests.

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